As semiconductor IC fabrication processing has developed, different wafer processing treatments have developed such as, for example, diffusion, oxidation, metalization, chemical vapor deposition (CVD) of thin films like epitaxial silicon and dielectric depositions like silicon dioxide and silicon nitride and ion implantation. Many of these treatments required heating of the wafer during treatment and removal of surface contaminants on the wafer before and/or after the treatments. Different methods and increasingly complicated physical structures have been developed and used for different treatments thereby complicating the semiconductor fabrication process, requiring more handling by personnel typically introducing contamination, increasing the time and space utilized in producing integrated circuits and often decreasing the yield.
Since the integrated circuit was first developed the complexity of the circuits has increased and the circuits have become more closely packed and more densely wired. The size of wafers on which the integrated circuits are made has steadily increased up to a current eight inches in diameter, and in many devices the processing steps have greatly increased in number. In 1983 a 64K (DRAM) Dynamic Random-Access-Memory device was manufactured on a four inch wafer with a minimum feature size of 2.5 to 4.0 micrometers using 132 process steps with 7 chemical vapor deposition steps and typically 18 wet chemical cleaning steps. Defects as small as 0.5 microns can have catastrophic effects on yield, and these defects can be caused by particulate contamination and/or defects in the thin films. Today a 4 MEG DRAM utilizes in excess of 150 process steps, a minimum feature size of less than 1.0 micrometers, in excess of 12 CVD process steps and more than 50 cleaning steps. The newer devices require less contamination, and people and chemicals contribute heavily to the contamination of semiconductor wafers.
Traditionally, chemical cleaning of wafers has involved immersion in a vat of hazardous chemicals in aqueous solution using a "wet deck" for a set amount of time. The wafers are removed from the bath, rinsed and spun dry. This sequence results in dilution of the bath and contamination of the device wafer due to exposure to air after each step. Scrubbing using brushes or high pressure fluid jets has been used in these wet processes. Newer cleaning processes have included centrifugal spraying and use of liquids flowing past the wafers.
Traditional wafer cleaning processes are not effective for removing contaminants in the manufacture of devices with a critical feature size of 3 microns or less. Cleaning chemistries in the liquid phase cannot reach into many miniaturized crevices and troughs typical of the geometry in the new generation of integrated circuits. After a wafer has been submerged in an industry-standard wet deck containing liquid cleaning chemistry, a droplet, influenced by surface tension, rests on top of the trough unable to remove contaminates in the trough and can deposit particulates and other contaminates there.
Environmental hazards are another major problem created by existing wet deck cleaning systems. The highly corrosive chemicals commonly used in traditional wet deck cleaning have proven to be hazardous to people and the environment.
A major source of contamination occurs in movement and storage of wafers from many of the processing steps into inventory of the partially processed wafer requiring individual cleaning steps before many of the subsequent treatment steps. This periodic movement of the wafer into and out of inventory adds to the chance of contamination and consequently reduced yield and contributes greatly to the expense of the equipment and manufacturing space required for producing a completed wafer.
With larger wafers and smaller critical feature sizes uniform heating of the wafer during the treatment steps has become more important. RF heating and radiant energy heating have been utilized. RF generators and infrared generators are expensive to manufacture and maintain as well as large in size, thereby consuming large areas of expensive floor space. The batch prosessing with these equipments added to the expense and potential contamination of IC fabrication. Still, these processes have resulted in non-uniformity of heating, especially with the larger diameter wafers being used to manufacture certain integrated circuits, and the methods and apparatus used for heating the wafer inhibited integration and automation of the various steps in fabrication of a semiconductor device wafer.